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Verilog Coding for Logic Synthesis


Verilog Coding for Logic Synthesis

Hardback by Lee, Weng Fook (Advanced Micro Devices (AMD) Design Center)

Verilog Coding for Logic Synthesis

WAS £131.95   SAVE £26.39

£105.56

ISBN:
9780471429760
Publication Date:
13 May 2003
Language:
English
Publisher:
John Wiley & Sons Inc
Imprint:
Wiley-Interscience
Pages:
309 pages
Format:
Hardback
For delivery:
Estimated despatch 6 - 8 May 2024
Verilog Coding for Logic Synthesis

Description

Provides a practical approach to Verilog design and problem solving. * Bulk of the book deals with practical design problems that design engineers solve on a daily basis. * Includes over 90 design examples. * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. * Book is suitable for use as a textbook in EE departments that have VLSI courses

Contents

Table of Figures. Table of Examples. List of Tables. Preface. Acknowledgments. Trademarks. Introduction. Asic Design Flow. Verilog Coding. Coding Style: Best-Known Method for Synthesis. Design Example of Programmable Timer. Design Example of Programmable Logic Block for Peripheral Interface.

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